Integrated circuits such as those found in computers and electronic equipment may contain millions of transistors and other circuit elements fabricated on a single crystal silicon chip. To achieve a desired functionality, a complex network of signal paths must be routed to connect the circuit elements distributed on the surface of the chip. Efficient routing of signals across a chip becomes increasingly difficult as integrated circuit complexity grows. To ease this task, interconnection wiring, which not too many years ago was limited to a single level of metal conductors, on today's devices may contain as many as five (with even more desired) stacked interconnected levels of densely packed conductors.
Conductor/insulator interconnect layers are typically formed by one of two general techniques. In the first technique, a conductive film is deposited over a preferably planar insulation layer (which usually contains vias, or through holes, allowing the conductive film to contact underlying circuit structure where electrical connections are needed). Portions of the conductive film are selectively etched away using a mask pattern, leaving a network of separate conductors with similar thickness and generally rectangular cross-section lying on the insulation layer. Usually, after patterning, the conductors are covered with an interlevel dielectric before additional conducting layers are added.
The second technique is known as damascene (after the inlaid metal technique perfected in ancient Damascus for decorating swords and the like), and involves etching a series of channels in the top surface of a preferably planar insulation layer and then depositing a conductive film over the etched insulation layer (preferably filling the channels with conductive material). A subsequent planarization, e.g. by chemical-mechanical polishing (CMP), removes the conductive film from the topmost surface of the insulation layer, but leaves conducting material in the channels, thereby forming a series of inlaid patterned conductors. This process is described in detail in U.S. Pat. No. 4,944,836, issued to Beyer et al. on Jul. 31, 1990.
Damascene is particularly attractive for submicron interconnect fabrication: chemical etching processes are known which can anisotropically (i.e. unidirectionally) etch insulators such as silicon dioxide to form high-aspect (i.e. deep and narrow) channels with vertical walls; it allows the use of low resistivity, high copper content conductive materials which cannot currently be patterned successfully by dry chemical etching; and, the process by nature results in planarized interconnection layers, which are highly desirable for multilevel interconnections.
An improved damascene process is claimed by Cote et al. in U.S. Pat. No. 5,262,354, issued on Nov. 16, 1993. Cote et al. cite several problems with damascene polishing used directly on low resistivity, soft metals such as Al-Cu alloys, including scratching, smearing, corrosion, and dishing (conducting material may be removed to a level below the top surface of the insulator). Their approach to this problem involves depositing the soft metal such that the channels are filled to between a few hundred nm and a few hundred .ANG. of the top surface of the dielectric, and capping this with a wear-resistant, higher resistivity layer (e.g. a refractory metal such as tungsten) before polishing. One difficulty with such an approach is the exacting control required for an anisotropic deposition of the soft metal to the required depth tolerance, particularly given normal variations in trench depth and metal deposition rate across a wafer. The higher resistivity refractory cap layer also results in an increase in resistance for all conductors fabricated on a given level, unless compensations in conductor height and/or width are incorporated in the design.